In the communication of electronic signals over networks, for example the Internet, or between high speed computers, it is often necessary to provide a buffer memory interface that provides short term storage of data being received prior to transmission of that data. The storage may be necessary to accommodate different communication protocols for the received and transmitted data, such as may include an underlying difference in data transmission rate, or may simply result from the asynchronous operation of the interconnected network and host devices.
Such buffer memory interfaces present a bottleneck to the rapid transfer of data so there is considerable interest in speeding the progress of data through the buffer memory.
In this regard, it is known to make use of a dual port random access memory (DPRAM) that permits simultaneous writing to and reading from the buffer memory of the interface as opposed to a sharing of a single set of data and address lines per conventional computer memory.
A buffer memory interface using a DPRAM may include two specialized interface circuits operating under the control of a dedicated microprocessor. The interface circuits handle the low-level protocols of communicating with the network and host devices joined by the buffer memory interface.
Many sophisticated high speed data transmission protocols transmit data in packets each containing a header identifying the packet to a longer message. Packetization of the data allows resources along the network to be pre-allocated to provide space for the receipt of the data and allow the media along which the data is transmitted to be more easily shared or multiplexed between different messages and packets. The header information allows the packets to be reassembled even if they don't arrive continuously or even in order.
For the receipt of packet data from a network, using a buffer memory interface, the microprocessor causes the network interface circuit of the buffer memory interface to issue a credit to the network device for a small amount of data--typically less than a full packet. According to a pre-established protocol, the network device then sends a data burst to the buffer memory interface, the burst including the header for a packet. This header is read by the microprocessor to determine the size of the packet and enough additional credits are issued to allow the entire packet to be received. The network interface circuit then handles the transfer of the data into the buffer memory for the number of credits issued after which time it interrupts the microprocessor. The microprocessor reads the word count collected by the interface circuit and moves a pointer in the DPRAM to be ready for the next packet. This process is repeated for each packet.
For the transmission of a packet of data from the host device to the network, the microprocessor first establishes a connection to the network device. It then calculates an address for the data on the network and sets a word count in a register of the network interface circuit. The network interface circuit then proceeds to transmit the data to the network device until the word count has been transmitted at which time it interrupts the microprocessor to set up a new transmission.
By using the microprocessor interrupt capabilities, the microprocessor coordinates its operation with the network and host interface circuits. Nevertheless the interrupt process is relatively inefficient requiring many machine cycles of the microprocessor during which time the data of the interrupted microprocessor task is saved and a new task for the interrupt is loaded. Importantly, as the present inventors have recognized, during the interrupt process the host or network interface circuits remain idle awaiting instructions from the microprocessor.
However, the use of a microprocessor provides great flexibility in the operation of the buffer memory interface, allowing it to be reprogrammed for use in different situations. In contrast, the interface circuits are usually realized as programmable array logic (PALs) providing for high speed operation, but limited reprogramming capability.